In the manufacture of semiconductor devices, a large number of semiconductor devices, also known as dice or integrated circuit chips (ICs or chips), are formed on a semiconductor wafer by using, for example, precision photolithographic technologies. These fabricated semiconductor devices are subjected to a series of test procedures in order to assess the electrical characteristics of the integrated circuits contained on the semicondutor devices. Semiconductor devices which have been found to be satisfactory by testing procedures are selectively transferred for subsequent processing such as die attach, wire bonding, and encapsulation. New integrated circuit designs and higher unit volumes are additional considerations that drive testing of ICs. Also, as IC devices become more complex, the need for high-speed and accurate testing becomes increasingly important.
IC device testing procedures conventionally include “wafer-level probe testing” in which individual ICs or groups of ICs, while still on the wafer, are initially tested to determine functionality and/or speed. Wafer probing establishes a temporary electrical contact between the IC and the automatic test equipment and is a critical step for verifying design and performance of the IC and for sorting ICs before singulation and costly packaging. Other tests, such as speed testing and “burn-in” testing are typically performed after the dice have been singulated from the wafer. IC testing further typically involves testing for various performance parameters while changing environmental conditions such as temperature, voltage and current.
Typically, testing at the wafer level involves the use of probe cards and other test heads to electrically test ICs by making electrical connection interfaces with groups of ICs or a single IC at a time. If the wafer has a yield of ICs which indicates that the quality and quantity of functional ICs is likely to be good, the individual ICs are singulated or “diced” from the wafer with a wafer saw. Each individual die may be assembled in a package to form an IC device, or may be bumped with solder (usually prior to separation from the wafer) for direct flip-chip bonding to a semiconductor substrate. Other various packaging means may also be used, as is known to those of skill in the art.
The test signals can include specific combinations of voltages and/or currents transmitted through the probe card to the ICs on the wafer. During the test procedure, response signals such as voltage, current and frequency are analyzed and compared to required values by a test controller. Thus, by applying the appropriate voltages and/or currents and monitoring the device response, a computer program running the testing apparatus determines the functionality of the die. The integrated circuits that do not meet specification can be marked or mapped in software. Following testing, defective circuits in the ICs may be repaired by actuating fuses (or anti-fuses) to inactivate the defective circuitry and substitute redundant circuitry.
Conventional probe cards can be generally classified into two categories: needle-type probe cards and membrane-type probe cards. Needle-type probe cards are the most common type of probe card, and include elongated probe needles mounted on an annular ring. A typical probe needle is a pointed needle-like element of small size, with a tip that tapers down into a sharp point. When mounted on the annular ring, the probe needles typically have their free ends pointing downward and are carefully aligned with the ends of all the other probe needles to be in a single plane. An exemplary probe needle configuration is disclosed in U.S. Pat. No. 5,532,613 to Nagasawa et al., which includes a probe needle having a pointed or conical tip. Probe needles are typically made of tungsten, but materials such as beryllium copper, palladium, and rhenium tungsten are also used.
The probe needles are typically secured to the annular ring by epoxy or are bonded, as by welding, to a blade, and are adapted to make temporary electrical connections between contact locations on the dice (e.g., bond pads, fuse pads, test pads) and external test circuitry. The annular ring, in turn, is attached to a printed circuit board (PCB) substrate. The PCB substrate typically includes electrical traces in electrical communication with the probe needles. An exemplary probe card having probe needles is described in U.S. Pat. No. 4,757,256 to Whann et al..
Membrane-type probe cards are typically formed as having tungsten contact bumps disposed on a thin, flexible dielectric material, such as polyimide, as the membrane. Membrane-type probe cards commonly employ a multilayer, flexible PCB interconnection structure configured with fine pitch traces leading to low inductance bump array structures aligned with the location of the pads of the device under test (e.g., a semiconductor die being tested). In a conventional membrane probing system, contact bumps of the bump array structures are pressed down via an elastic body interposed between the contact bumps and the membrane, such that any height variation among the contact bumps can be absorbed by the flexible thickness of the elastic body. Exemplary membrane-type probe cards are disclosed in U.S. Pat. No. 4,906,920 to Huff et al. and in U.S. Pat. No. 6,181,145 to Tomita et al..
Needle-type probe cards and membrane-type probe cards may be further configured to meet the needs of the particular devices under test. In this regard, the probe cards may be specially configured as vertical contact probe cards (used, for example, to test LOGIC devices of a C4 type), cantilever-type probe cards (generally used to test inner-leads of LCD drivers with super fine-pitch (e.g., 40 micron-pitch) bumps), probe cards for wafer level burn-in, probe cards configured to test high-speed microprocessor units (MPUs) with high pin counts, as well as various other types of probe cards known in the art.
In all types of probe cards, the testing voltage current is carried from an external test circuit to the pad connecting sections (probe elements) of the probe cards through conductive traces or wiring in electrical communication therewith.
One concern in the art is over the application of excessive voltage to the IC chip under test. In this regard, U.S. Pat. No. 6,127,837 to Yamamoto et al. (“Yamamoto”) describes a series of resistance, transistor and capacitance structures formed on a probe wafer between a test bump and a shared power/signal line. According to Yamamoto, the resistance, transistor and capacitance structures prevent overshoot or undershoot of signals supplied to the bump, and also prevent the application of excessive voltage or current to the chip. Yamamoto, however, does not disclose methods or apparatus for protection of the probe wafer, and further does not describe a probe card configured to carry the current regulating structures.
The delivery of excessive voltage during probe testing to an IC may also result in damage to the probe card. In Japanese Patent Application 61174771, a small fuse is provided on the back side surface of a probe card in order to prevent the end of a probe needle connected to a grounding pad from seizing due to an over-current delivered to a short circuited IC. Japanese Patent Application 0115367 discloses a thermal fuse fixed between a probe needle and power source which generates heat and becomes fused before a probe pin generates heat and is fused. Each of these patent applications, however, is drawn to means for preventing seizing and fusing of a probe needle routed to ground and power, and do not address the limitation of current through the probe card in general or through any probe needle which might otherwise cause that probe needle to become nonfunctional.
Japanese Patent Application 04265541 discloses an array of easily exchanged fuses interposed between corresponding probes on a probe card and a power supply. The apparatus disclosed therein, however, is relatively bulky in that the fuses are vertically disposed over the probe card and the apparatus includes a fuse body for holding the fuses.
Accordingly, what is needed in the art is a probe card configuration designed to limit current to a plurality of varying probe elements, not just ground and power. It would also be advantageous to provide a probe card with one or more fuses that are self-resetting, or readily replaceable and/or repairable. Fuses which can be fabricated simultaneously with other components on the probe card using processes which are well known in the semiconductor arts are also desirable. A probe card thus manufactured would extend the life of the probe card, therefore, saving time, materials, and costs for those involved in semiconductor dice testing operations.